Complicated system on a chip (SoC), application-specific integrated circuits (ASICs) and application-specific signal processors (ASSPS) often are large and employ significant amounts of on-chip random-access memory (RAM). Such a large circuit means that the smallest possible geometry fabrication process should be used to achieve a die size that is cost effective for manufacture. However, conventional bit cells of a RAM are optimised aggressively for a minimum cell area. It is often the case that integrated circuits with large amounts of on-chip RAM are vulnerable to fabrication errors when a small geometry fabrication process is used. Fabrication yields can be unacceptably low, especially while an immature fabrication process is tuned. Low yield of an integrated circuit product that has an inherently large die size results in excessively high manufacturing costs.